Optical emission spectroscopy (OES) spectra have been used for plasma dry etch processes to determine an etch endpoint. For example, when an etch process passes through a first material layer into a second material layer having different component materials, a sudden change in the OES spectral content can often be seen. This sudden change can be used as an etch endpoint indicator. Identifying a proper etch endpoint helps to control the amount of etching that occurs into stop layers during the etch process. However, even with more precise endpoint control, etch processes can still lead to undesirable variations in line width, line edges, and critical dimension (CD) of patterned features formed during the etch process. Example OES systems and methods are described in U.S. Pat. Nos. 5,980,767, 6,677,604, and U.S. Published Patent Application No. 2005/0173375, each of which is hereby incorporated by reference in its entirety.
FIG. 1A (Prior Art) is a flow diagram of an example embodiment 100 for a manufacturing process including an etch process, for example, that uses OES endpoint control. In block 102, a resist (e.g., photoresist) layer is formed on a substrate for a microelectronic workpiece, and the substrate can include one more previously formed layers and/or structures. In block 104, a pre-treatment process is applied to the resist layer using standard process parameters. The pre-treatment can include, for example, an electron beam (e-beam) resist surface modification pre-treatment utilizing the application of upper electrode DC superposition (DCS) voltage. In block 106, an etch process is performed to generate patterned structures, for example, using OES endpoint control. This etch process in part uses the resist layer to form the patterned structures. Example systems and methods that utilize DCS pre-treatment are described in U.S. Patent No. 2015/0160557, which is hereby incorporated by reference in its entirety.
FIG. 1B (Prior Art) is an example embodiment 150 for patterned structures including line structures 154 formed using the steps of FIG. 1A (Prior Art) on a substrate 152 for a microelectronic workpiece. The line structures 154 can include one or more layers. Variations within the line structures 154 can lead to subsequent problems with microelectronic devices formed with respect to the substrate 152. These variations include CD variations in the bottom surfaces 156 of trenches between the line structures 154, line width variations for the widths 158 of the line structures 154, and line edge variations for the edges 160 of the line structures 154. CD variations, line-width roughness (LWR), and line-edge roughness (LER) are parameters often used to evaluate the success of etch processes and/or other surface modification processes. Typically, it is desirable to reduce CD variations, LER, and LWR in patterned structures formed within substrates for microelectronic workpieces. Other etch metrics can also be monitored and/or measured with respect to etch processes.